Ecological appropriation of Joel

Most modern ecological-hermeneutical approaches to biblical interpretation of prophetic texts have concentrated on identifying the ecological significance of the text in its original historical context. Given the urgency of concerns about the modern ecological crisis, there is also a need to use scripture to assist in development of contemporary environmental ethics within an industrialised society. This paper describes a technique called ecological appropriation which seeks to take a biblical text, in this case the book of Joel, and apply its message to modern ecological concerns, whilst still preserving its fundamental theological message. This technique yields new insights into an appropriate, biblically-inspired response to the ecological crisis which involves key steps of acknowledgement, mourning, repentance, judgement, return to God, and restoration

An analysis of FPGA-based custom computers for DSP applications

Field programmable gate arrays (FPGAs) can be rapidly reconfigured to provide different digital logic functions. When such FPGA logic circuits are incorporated within a stored-program computer, the result is a machine where the programmer can design both the software and the hardware that will execute that software. This paper first surveys this area of custom computing. It then describes a new custom computing architecture which uses a processing node with three sections: a standard arithmetic chip, static RAM and reconfigurable logic for operand handling. Finally an analysis of the suitability of this new approach for implementation of DSP applications shows it to be worthy of further investigation

Architecture design of a fully asynchronous VLSI chip for DSP custom applications

A fully asynchronous, distributed VLSI architecture is introduced for dedicated real-time digital signal processing applications. The architecture is based on a data-driven computing model to allow maximum exploitation of the fine-grained concurrency. An asynchronous, self-time signaling protocol is used in the architecture to naturally match data-driven computing and circumvent the clock skew problem. After a brief description of the architecture, key issues of the architecture, such as the interconnection network, data identification, and operand matching are discussed. Finally, disadvantages of the architecture and future work are outlined

Comparing the performance of FPGA-based custom computers with general-purpose computers for DSP applications

When FPGA logic circuits are incorporated within a stored-program computer, the result is a machine where the programmer can design both the software and the hardware that will execute that software. This paper first describes some of the more important custom computers, and their potential weakness as DSP implementation platforms. It then describes a new custom computing architecture which is specifically designed for efficient implementation of DSP algorithms. Finally, it presents a simple performance comparison of a number of DSP implementation alternatives, and concludes that the new custom computing architecture is worthy of further investigation, and that custom computers based only on FPGA execution units show little performance improvement over state-of-the-art workstations

A hardware scheduler based on task queues for FPGA-based embedded real-time systems

A hardware scheduler is developed to improve real-time performance of soft-core processor based computing systems. A hardware scheduler typically accelerates system performance at the cost of increased hardware resources, inflexibility and integration difficulty. However, the reprogrammability of FPGA-based systems removes the problems of inflexibility and integration difficulty. This paper introduces a new task-queue architecture to better support practical task controls and maintain good resource scaling. The scheduler can be configured to support various algorithms such as time sliced priority scheduling, Earliest Deadline First and Least Slack Time. The hardware scheduler reduces scheduling overhead by more than 1,000 clock cycles and raises the system utilization bound by a maximum 19.2 percent. Scheduling jitter is reduced from hundreds of clock cycles in software to just two or three cycles for most operations. The additional resource cost is no more than 17 percent of a typical softcore system for a small scale embedded application

QUKU: A Coarse Grained Paradigm for FPGAs

To fill the gap between increasing demand for reconfigurability and performance efficiency, CGRAs are seen to be an emerging platform. The advantage lies in quick dynamic reconfiguration and power efficiency. Despite having these advantages they have failed to show their mark. This paper describes the QUKU architecture, which uses a coarse-grained dynamically reconfigurable PE array (CGRA) overlaid on an FPGA. The low-speed reconfigurability of the FPGA is used to optimize the CGRA for different applications, whilst the high-speed CGRA reconfiguration is used within an application for operator re-use

Multi-mode Tracking of a Group of Mobile Agents

We consider the problem of tracking a group of mobile nodes with limited available computational and energy resources given noisy RSSI measurements and position estimates from group members. The multilateration solutions are known for energy efficiency. However, these solutions are not directly applicable to dynamic grouping scenarios where neighbourhoods and resource availability may frequently change. Existing algorithms such as cluster-based GPS duty-cycling, individual-based tracking, and multilateration-based tracking can only partially deal with the challenges of dynamic grouping scenarios. To cope with these challenges in an effective manner, we propose a new group-based multi-mode tracking algorithm. The proposed algorithm takes the topological structure of the group as well as the availability of the resources into consideration and decides the best solution at any particular time instance. We consider a clustering approach where a cluster head coordinates the usage of resources among the cluster members. We evaluate the energy-accuracy trade-off of the proposed algorithm for various fixed sampling intervals. The evaluation is based on the 2D position tracks of 40 nodes generated using Reynolds' flocking model. For a given energy budget, the proposed algorithm reduces the mean tracking error by up to $20\%$ in comparison to the existing energy-efficient cooperative algorithms. Moreover, the proposed algorithm is as accurate as the individual-based tracking while using almost half the energy.Comment: Accepted for publication in the 20th international symposium on wireless personal multimedia communications (WPMC-2017

RSSI-Based Self-Localization with Perturbed Anchor Positions

We consider the problem of self-localization by a resource-constrained mobile node given perturbed anchor position information and distance estimates from the anchor nodes. We consider normally-distributed noise in anchor position information. The distance estimates are based on the log-normal shadowing path-loss model for the RSSI measurements. The available solutions to this problem are based on complex and iterative optimization techniques such as semidefinite programming or second-order cone programming, which are not suitable for resource-constrained environments. In this paper, we propose a closed-form weighted least-squares solution. We calculate the weights by taking into account the statistical properties of the perturbations in both RSSI and anchor position information. We also estimate the bias of the proposed solution and subtract it from the proposed solution. We evaluate the performance of the proposed algorithm considering a set of arbitrary network topologies in comparison to an existing algorithm that is based on a similar approach but only accounts for perturbations in the RSSI measurements. We also compare the results with the corresponding Cramer-Rao lower bound. Our experimental evaluation shows that the proposed algorithm can substantially improve the localization performance in terms of both root mean square error and bias.Comment: Accepted for publication in 28th Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (IEEE PIMRC 2017

Embedded Linux as a Platform for Dynamically Self-Reconfiguring Systems-On-Chip

We have previously argued the benefits of embedded Linux as an operating system platform for reconfigurable system-on-chip design. In this paper we describe our approach to building tools for the implementation of dynamically and self-reconfigurable systems, and show that embedded Linux is a natural and powerful platform on which to build these tools. We present examples and demonstrations that show how complex operations such as obtaining partial bit streams from remote servers and initiating reconfiguration are achieved with a single line of Linux shell script